The present invention relates to a semiconductor device having a structure achieved by bonding inner leads to a semiconductor element internally provided at a package.
The memory capacities in semiconductor devices such as memory units have been increasing, as in 16 Mb DRAM and 64 Mb DRAM in recent years, which has resulted in an increase in the size of the semiconductor element (chip) which is internally provided at the package. At the same time, there is a need for miniaturization of semiconductor devices to facilitate high density mounting in electrical products, and thus, a large semiconductor element must be mounted in a small package. As a means for achieving this, LOC (Lead On Chip) semiconductor devices having a structure achieved by using double-sided adhesive tape to directly bond inner leads to a front surface of a semiconductor element and packaging this with resin have been proposed.
FIG. 17 is a plan view illustrating the internal structure of an LOC semiconductor device 100 in the prior art. FIG. 18 is a cross section along line D_D in FIG. 17. A plurality of inner leads 104 are bonded using a double-sided adhesive tape 103 having an insulating property at a front surface of a semiconductor element (chip) 102 covered by a package 101. The inner leads 104 are each electrically connected with an electrode pad 105 provided at the front surface of the semiconductor element 102 via a wire 106 such as a metal wire. In addition, the assembly is sealed (molded) with liquid resin inside a forming die in a state in which the inner leads 104 are bonded to the front surface of the semiconductor element 102 to achieve a structure having the semiconductor element 102 internally provided in the package 101. With the semiconductor device 100 having such an LOC structure, which does not require a die bat or the like for supporting the semiconductor element 102 unlike conventional packages, a relative increase can be achieved in the rate of the volume occupied by the semiconductor element 102 in the package 101 to realize miniaturization and high density mounting. Ultimately, with a semiconductor device 100 having the LOC structure, the ratio of the volume occupied by the semiconductor element 102 within the package 101 can be increased up to a maximum of approximately 90%.
However, in a semiconductor device having the LOC structure, the semiconductor element may be sometimes caused to move vertically within the forming die by the pressure of the liquid resin used for sealing and the like, resulting in the semiconductor element being placed at a position offset from the center inside the package. Such a misalignment of the semiconductor element is referred to as a chip shift. In the case of a semiconductor device having a so-called TSOP (Thin Small Outline Package) structure which employs a thin package, in particular, misalignment of the semiconductor element (chip shift) is problematic, since it may cause exposed wires and forming defects such as incomplete sealing of the package, which, in turn, will result in a reduction in the moisture resistance and the like.